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L5953
MULTIPLE SWITCHING VOLTAGE REGULATOR
PRODUCT PREVIEW
s s s s
s
s s s s s s
PWM: ADJUSTABLE 2.5/10V - 1A SWITCHING VOLTAGE REGULATOR EXTERNAL POWER MOS ABILITY FOR OUTPUT CURRENT ENHANCEMENT SYNCHRONIZATION FUNCTION REG1- LINEAR LOW DROP 3.3/5V - 250mA STBY VOLTAGE REGULATOR (LOW CURRENT CONSUMPTION) with RESET REG2- LINEAR VOLTAGE REGULATOR 1.5V to 3.3V EXTERNALLY ADJUSTABLE - 300mA MAXIMUM CURRENT HSD1 : 500mA HIGH SIDE DRIVER HSD2 : 200mA HIGH SIDE DRIVER SPI INTERFACE SPI DIAGNOSTICS HSD1, HSD2 DOUBLE SWITCHING FREQUENCY SPI SELECTABLE DOUBLE INPUT LVW
PowerSO36 ORDERING NUMBER: L5953
- HSD1 & HSD2 short to gnd, open load and short to battery (Test mode) - Thermal warning PROTECTIONS s OVERVOLTAGE PROTECTION s INTERNAL CURRENT LIMITING s THERMAL SHUTDOWN s ESD DESCRIPTION The L5953 is the integration of one switching regulator, two linear voltage regulators, two low voltage warnings and two high side drivers. It has a stand-by operation mode (low current consumption) where only the stand-by voltage regulator plus the low voltage warnings are active. The other regulators and high side drivers are controlled by the SPI interface.
SPI FUNCTIONS s INPUT CONTROLS - Turn-on/off PWM - Turn-on/off REG2 - Turn-on/off HSD1 - Turn-on/off HSD2 - Switching frequency selection f1- f2 s OUTPUT FUNCTIONS: BLOCK DIAGRAM
S1 W1 S2 W2 VDD-LIN VDD-SW
STCAP
CT
RES FGND
VOLTAGE WARNING
REC1 ST-BY LINEAR VOLTAGE REGULATOR 3.3-5V/250mA
VSTBY ADJ
HSD1 HSD1 PWM STEP DOWN REGULATOR 2.5-10V/1A STRAP
HSD2 HSD2
DRAINOUT
VSW GATEIN GATEOUT FB REC2 LINEAR VOLTAGE REGULATOR 1.5-3.3V/300mA COMP OSCILLATOR & SYNC
VSPI IRQ
SPI INTERFACE
SWGND GND
Q
D
S
C
VLR
FBLR
VIN
SYNC
DGND
D01AU1330A
September 2003
This is preliminary information on a new product now in development. Details are subject to change without notice.
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L5953
ABSOLUTE MAXIMUM RATINGS
Symbol VDD Parameter DC Operating Supply Voltage Transient Supply Overvoltage (250ms) VSPI IO Vinlog RESR Top Tstg Tj Supply Voltage for SPI I/O Voltage Regulator Output Current Input Voltage (C,D,Q,S,SYNC) Output Capacitor Series Eq. Resistance (Linear reg.)(Allowed range) Operating Temperature Range Storage Temperature Ranges Operative Junction Temperature Value -0.6 to 30 50 -0.6 to 6 Internally limited 0 to 6 From 0.2 to 10 -40 to 85 -55 to 150 -40 to 150 V C C C Unit V V V
THERMAL DATA
Symbol Rthj-case Parameter Thermal Resistance Junction to Case Value 1.7 Unit C/W
PIN CONNECTION
FGND S2 S1 W2 W1 RES CT D C Q S DGND IRQ HSD2 VDD-LIN N.C. HSD1 SWGND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
D02AU1345A
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
ADJ VSTBY VSPI STCAP FB COMP FBLR VIN VLR SYNC STRAP GATEOUT GATEIN VSW GND N.C. DRAINOUT VDD-SW
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L5953
PIN FUNCTION
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 FGND S2 S1 W2 W1 RES CT D C Q S DGND IRQ HSD2 VDD-LIN N.C. HSD1 SWGND VDD-SW DRAINOUT N.C. GND VSW GATEIN GATEOUT STRAP SYNC VLR VIN FBLR COMP FB STCAP VSPI VSTBY ADJ Pin Name Analog Ground Input Voltage for LVW2 Input Voltage for LVW1 LVW2 Output LVW1 Output Reset Timing capacitor SPI Serial Input SPI Clock SPI Serial Output SPI Chip Select SPI Ground Interrupt HSD2 Output Battery Not Connected HSD1 Output Switching Ground PWM Battery Drain of the exrternal MOS Not Connected Ground Source of the external MOS Gate of the internal MOS Switching Output for power mos gate Bootstrap Synchronization REG2 Linear Voltage Regulator Output REG2 Linear Voltage Regulator Input REG2 Linear Voltage Regulator Feedback PWM Compensation PWM Feedback ST-CAP Supply Voltage for SPI I/O REG1 Stand-by Linear Voltage Regulator Output 3.3V/5V REG1 Voltage Select Function
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L5953
ELECTRICAL CHARACTERISTCS ( Tamb = 25C, VDD = 14.4V)
Symbol IQ,STBY Parameter Quiescent current with regulators and High-side drivers off Test Condition W1, W2, RES, IRQ, not active; REG2, HSD1, HSD2, PWM off; S, C, D fixed at high/low logic level 150 Min. Typ. Max. 100 Unit A
Tsd
Thermal Shutdown Junction Temperature
C
SMPS.PWM
Tamb = 25C, VDD = 14.4V, Vo = 5V; unless otherwise specified.)
Vo,min Vo,max Vref,PWM Vi Vo Vo Vd Minimum Output Voltage Maximum Output Voltage Voltage Reference Input Voltage Range Line Regulation Load Regulation Dropout Voltage between Pin 19 and Pin 23 Current Limit Efficiency f = 260kHz; Io = 0.5A f = 400kHz; Io = 0.5A Vi = 1Vrms; fripple = 300Hz; Io = 0.4A Vo = 5V; Io = 0.5A Io = 0.5A Vo = 5V; Io = 0.2A to 0.5A Io = 0.5A, Vo = 5V Io = 1A, Vo = 5V ILim SVR 1.5 90 86 50 6 Io = 200mA Io = 200mA 2.4 9.6 2.5 10 1.275 18 100 50 0.5 1 2.6 10.4 V V V V mV mV V V A % % dB
Supply Voltage Ripple Rejection
OSCILLATOR f1 f2 f-------V i f-------T j SYNC VIL VIH VOL VOH Low Input Voltage High Input Voltage Low Output Voltage High Output Voltage ISOURCE=1.5mA 4 2 0.4 0.8 V V V V Swiching frequency Swiching frequency Voltage Stability of Switching Frequency Temperature Stability of Switching Frequency VDD = 8 to 18V 249 384 260 400 Tbd 271 416 kHz kHz %
Tj = -40C to 85C
Tbd
%
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L5953
ELECTRICAL CHARACTERISTCS (continued) ( Tamb = 25C, VDD = 14.4V)
Symbol ISLAVE TW Parameter Slave Sink Current Output Pulse Width Test Condition Min. Typ. 100 300 Max. Unit A ns
REG1 - 3.3V/5V STBY LINEAR VOLTAGE REGULATOR VSTBY Vline Vload Vdropout Ilim SVR Output Voltage Line Regulation Load Regulation VSTCAP - VSTBY Current Limit Supply Voltage Rejection no load; ADJ pin = open no load; ADJ pin = VSTBY pin no load; 7 < Vdd < 26V 5mA < Io < 250mA Io = 100mA, Vo = 5V Io = 100mA, Vo = 3.3V Out short to GND VDD = 1Vrms: f = 300Hz Io = 250mA 300 55 4.9 3.20 5 3.3 5 12 0.36 0.47 5.1 3.4 50 80 0.5 0.65 V V mV mV V
mA dB
REG2 - LINEAR VOLTAGE REGULATOR 1.5V to 3.3V VLR Linear Regulator Output Voltage no load; 4.75 VIN 16V; 1+ (R5/R6) = 2.588 no load; 3.135 VIN 16V; 1+ (R5/R6) = 1.176 VIN Input Voltage IO = 150mA 1.5V VLR 2V IO = 300mA 1.5V VLR 3.3V Vload Vline Load Regulation 5mA IO 300mA 4.75V VIN 16V; 1.5V VLR 3.3V no load; 4.75V VIN 16V; 1.5V VLR 3.3V 3.2 1.45 3.135 3.3 1.5 3.4 1.55 16 V V
4.75
16
V
12
mV
Line Regulation
1 1.275
mV V mA
Vref,REG2 Voltage Reference ILim SVR Current Limit Supply Voltage Rejection Out Short to ground VIN = 5Vdc, 0.5Vacpp, 300Hz IO = 300mA; 1.5V VLR 3.3V VIN = 3.3Vdc, 0.5Vacpp, 300Hz IO = 150mA; 1.5V VLR 2V HSD1 Vsat, peak Saturation Voltage Ilim Lload Current Limit Load Inductance IO = 0.5A 600 400
55
dB
55
dB
250
mV mA
100
mH
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L5953
ELECTRICAL CHARACTERISTCS (continued) ( Tamb = 25C, VDD = 14.4V)
Symbol HSD2 Vsat, peak Saturation Voltage Ilim Lload Current Limit Load Inductance IO = 0.2A 300 100 250 mV mA mH Parameter Test Condition Min. Typ. Max. Unit
VOLTAGE WARNING Vst Vsth VSL ISH ISI RESET VRT VRTH VRL IRH VCTth VCThy ICT1 RCT2 Reset Threshold Voltage Reset Threhold Hysteresis Reset Output Voltage Reset Output Leakage Delay Comparator Threshold Delay Comparator Threshold Hysteresys Timing Capacitor Output Source Current Timing Capacitor Output PullDown equivalent Resistor Io = 1mA VRT = VSTBY 0.5 x VSTBY 180 7.5 150 mV A 0.95 x VSTBY 0.02 x VSTBY 0.4 10 V V V A Sense Low Threshold Sense Threshold Hysteresis Sense Output Low Voltage Sense Output Leakage Sense Input Current Io = 1mA VW = 5V; VSI 1.5V VSI=5V 1 1.245 35 1.275 45 1.305 60 0.4 10 V mV V A A
DIAGNOSTIC PARAMETERS
Symbol Parameter Test Condition Min. Typ. 0.95 HSD1 output voltage in test mode HSD1 in test mode Measure VVDD-LIN-VHSD1 3 1.5 0.7 Max. Unit A V V A
HSD1W1 High Side Driver 1 Overcurrent Warning activation HSD1W2 High Side Driver 1 Open Load Warning activation HSD1W2 High Side Driver 1 VDD Short TEST Warning activation in test mode HSD2W1 High Side Driver 2 Overcurrent Warning activation
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Symbol Parameter Test Condition HSD2 output voltage in test mode HSD2 in test mode Measure VVDD-LIN-VHSD1 Min. Typ. 3 1.5 145 Max. Unit V V C
HSD2W2 High Side Driver 2 Open Load Warning activation HSD2W3 High Side Driver 2 VDD Short Warning activation in test mode THW Thermal warning activation
IRQ - Interrupt Request Pin IRQ-L IRQ-H IRQ Low voltage IRQ Leakage Io = 1mA Virq = 5V 0.4 1 V A
SPI INTERFACE
Symbol Alt Parameter Test Conditions Min. Max. Unit
Recommended DC Operating Voltage VSPI Supply Voltage for SPI I/O 3 5.5 V
Input Parameters (Tamb = 25C, f = 1MHz) CIN CIN tLPF Input Capacitance (D) Input Capacitance (others pins) Input Signal Pulse Width 8 6 10 pF pF ns
DC Characteristics (Tamb = -40 to 85C, VSPI = 3V to 5.5V) ILI ILO VIL VIH VOL VOH Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 2mA IOH = -2mA 0.8VSPI -0.3 0.7VSPI 2 2 0.3VSPI VSPI+1 0.2VSPI A A V V V V
AC Characteristics (Tamb = -40 to 85C, VSPI = 3V to 5.5V tSCLH tCLSH tCH tCL tCLCH tCHCL tDVCH tCHDX tDLDH tSU tSH tWH tWL tRC tFC tDSU tDH tRI S Setup Time S Hold Time Clock High Time Clock Low Time Clock Rise Time Clock Fall Time Data In Setup Time Data In Hold Time Data In Rise Time 50 50 1 50 50 200 300 1 1 ns ns ns ns s s ns ns s
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L5953
Symbol tDHDL tSHSL tSHQZ tQVCL tCLQX tQLQH tQHQL Alt tFI tCS tDIS tV tHO tRO tFO Parameter Data in Fall Time S Deselect Time Output Disable Time Clock Low to Output Valid Output Hold Time Output Rise Time Output Fall Time 0 100 100 4.5V < VSPI < 5.5V 3V < VSPI < 4.5V 200 250 150 250 Test Conditions Min. Max. 1 Unit s ns ns ns ns ns ns ns
Figure 1. AC Testing Input Output WaveformsI
0.8VSPY 0.7VSPY
0.2VSPY
0.3VSPY
D03AU1479
Figure 2. SPI Clocking Scheme
S
(MODE 0: CPOL=0,CPHA=0)
C
C
(MODE 3: CPOL=1,CPHA=1)
D Q
MSB
6
5
4
3
2
1
0
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L5953
Figure 3. Output Timing
S tCH C tCLQX tQVCL Q MSB OUT MSB-1 OUT tQLQH tQHQL D
ADDR.LSB IN
tCL
tSHQZ
LSB OUT
(CPOL=0, CPHA=0)
AI01070B
Figure 4. Serial Input Timing
tSHSL S tSLCH C tDVCH tCHDX D MSB IN tDLDH tDHDL tCLCH LSB IN tCHCL tCLSH
HIGH IMPEDANCE Q
(CPOL=0, CPHA=0)
AI01071
FUNCTIONAL DESCRIPTION REG1 Stand-by Regulator (Figure 5) The stand-by regulator output voltage can be 5V or 3.3V. It is externally selectable by means of the ADJ pin: - leaving the ADJ pin open, the output voltage is 5V; - connecting the ADJ pin to the Vstby pin the output voltage becomes 3.3V. This regulator is supplied by STCAP pin and provide the reset information. It has a current protection which limits the maximum allowable output current. Reset (Figure 6) The RES pin is an open collector that is activated (that is forced to zero) when the stand-by regulator is not in regulation (including thermal shutdown and faults). The indication that REG1 is in regulation is delayed by a time
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L5953
set up by the external capacitor CT. When the RES is switched on, HSD1, HSD2, REG2, PWM are turned off and until the RES is forced to zero only the REG1 and low Voltage Warnings are active. Low Voltage Warning(Figure 7) This circuit is able to sense two different voltages through external resistors to increase the overall flexibility. If S1 pin voltage is higher than Vst, the output mos M1 is off: W1 is floating and can be pulled up by an external resistor. If S1 pin voltage goes down and becomes lower than Vst, the mos M1 is turned on and forces W1 to zero. The same thing happens for S2 - W2. The outputs W1 and W2 can be connected together to get a single output. REG2 Linear Voltage Regulator (Figure 5) REG2 is a linear voltage regulator with a dedicated supply pin VIN. The output voltage (between 1.5V and 3.3V) is fixed by an external divider. It can be turned on/off by SPI. It has a current protection which limits the maximum allowable output current. High Side Drivers (Figure 8) Two high-side driver with charge pump controlled by SPI are available inside L5953. They are protected against short to ground: the short circuit potection limits the maximum output current. A diagnostic procedure is available to detect open load, short to battery and overcurrent. Open load and short to battery can be reveal only in test mode while overcurrent is active only during normal operationof the device. (see OPERATION -page 13 PWM Step Down Voltage Regulator (Figure 9) The switching regulator inside the L5953 is a voltage control mode (also known as "direct duty cycle") Buck regulator: the error signal coming from the error amplifier is compared with a sawtooth to set on and off times of the power switch. The feedforward control is introduced to get a quickly response to input voltage changes: the sawtooh has a fixed frequency and an amplitude variable with the battery voltage. Continuous mode operation is recommended in order to reduce the stress of the output capacitor and of the free-wheeling diode. Error amplifier and compensation network The error amplifier (EA) is a voltage amplifier whose non-inverting input is fixed to the reference voltage (1.275V bandgap voltage) and whose inverting input and output are externally available for feedback and frequency compensation.
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L5953
Figure 5. Linear regulators - Internal pin connections
STCAP VREF 1.275V VSTBY CONTROLLER POWER MOS VSTBY VSTBY
ADJ
FGND FBLR VLR
LINEAR REGULATOR CONTROLLER VREF 1.275V POWER MOS
VIN
D03AU1493
Figure 6. Reset Internal pin Connection
7.5A
Vref 2.5V/1.65V
RES
CT
FROM VST-BY Vref 1.275V
D03AU1480
Figure 7. Low Voltage Warning Block Diagram.
V1 Vref =1.275V S1 W1 + M1
V2 Vref =1.275V S2 W2 + M2
D03AU1478
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L5953
Figure 8. HSD - Internal pin connections
HSD1 HSD1 CONTROLLER POWER MOS HSD1 VDD-LIN HSD2 CONTROLLER POWER MOS HSD2 HSD2
D01AU1333
Figure 9. PWM - Internal pin connections
STRAP ERROR AMPLIFIER COMP FB VDD-SW
RS2 CURRENT SENSING DRAINOUT RS1
VREF 1.275V PWM CONTROLLER FROM THE OSCILLATOR POWER MOS
VSW
GATEIN GATEOUT
D03AU1482
Figure 10. SPI & IRQ Internal pin connections
IRQ S Q SPI INTERFACE D C DGND
D03AU1481
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L5953
SPI INTERFACE Signals Description (Figure 10) The SPI interface available inside L5953 is able to work both in Mode 0 and Mode 3. Serial Output (Q). The output pin is used to transfer data serially out of the L5953. Data is shifted out on the falling edge of the serial clock. Serial Input (D). The input pin is used to transfer data serially into the device. It receives instructions, addresses, and data to be written. Input is latched on the rising edge of the serial clock. Serial Clock (C). The serial clock provides the timing of the serial interface. Instructions, addresses, or data present at the input pin are latched on the rising edge of the clock input, while data on the Q pin changes after the falling edge of the clock input. Chip Select (S). This input is used to select the L5953. The chip is selected by a high to low transition on the S pin. At any time, the chip is deselected by a low to high transition on the S pin. As soon as the chip is deselected, the Q pin is at high impedance state. The pin allows multiple L5953 to share the same SPI bus. After power up, the chip is at the deselect state. SPI Input/Output are supplied by an external supply voltage VSPI while the core is supplied by the stand-by regulator VSTBY. The SPI is resetted by an internal signal whose buffered version is RES . OPERATIONS All instructions, addresses and data are shifted in and out of the chip MSB first. Data input (D) is sampled on the first rising edge of clock (C) after the chip select (S) goes low. Prior to any operation, a one-byte instruction code must be entered in the chip. This code is entered in the chip. This code is entered via the data input (D), and latched on the rising edge of the clock input (C). To enter an instruction code, the product must have been previously selected (S = low). Table 1 shows the instruction set and format for device operation. An invalid instruction (one not contained in table 1) leaves the chip as previously selected. Write Enable (WREN and Write Disable (WRDI) The L5953 contains a write enable latch. This latch must be set prior to every WRITE operation. The WREN instruction will set the latch and the WRDI istruction will reset the latch. The latch is reset under all the following conditions: - Power on - WRDI instruction executed As soon as the WREN or WRDI instruction is received by the L5953, the circuit executes the instruction and enters a wait mode until it is deselected. Table 1. Instruction Set.
Instruction WREN WRDI WSTA RDIA RSTA Description Set Write Enable Latch Reset Write Enable Latch Write Status Register Read Diagnostic Register Read Status Register Instruction Format 00000110 00000100 00000010 00000101 00000011
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L5953
Table 2. Status Register.
s15 s14 s13 HSD2 s12 TBD s11 TBD s10 s9 s8 TBD s7 TBD s6 TBD s5 TBD s4 TBD s3 TBD s2 TBD s1 s0
REG2 HSD1
PWM PWM Freq.
Test START Mode DIAG
Table 3. Status Register Description
0 s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 REG2 Linear Voltage Regulator 1.5 to 3.3V High Side Driver 1 High Side Driver 2 TBD TBD PWM switching frequency PWM Voltage Regulator TBD TBD TBD TBD TBD TBD TBD Test Mode s1 Test Mode off Test Mode on NOTE: in this case the bits s15 - s2 are internally set to 0 (regulators and high side drivers are in off condition) Starts the diagnostic procedure: - in Test Mode if s1=1; - during normal operation if s1=0 If s1=0 and s0=1, must be s14 = 1 (HSD1 ON) and s13=1 (HSD2 ON) 260kHz PWM1 off 400kHz PWM1 on Regulator off HSD1 off HSD2 off Regulator on HSD1 on HSD2 on 1
Diagnostic s0
Diagnostic off
Table 4. Diagnostic Register.
d7 Test mode d6 HSD1W1 d5 HSD1W2 d4 HSD1W3 d3 HSD2W1 d2 HSD2W2 d1 HSD2W3 d0 THW
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L5953
Table 5. Diagnostic Register Description.
0 d7 Test mode The Diagnostic Register is referred to a test performed during the normal working of the L5953 If d7=0: HSD1 in normal condition; If d7=1: bit value meaningless If d7=0: bit value meaningless; If d7=1: HSD1 in normal condition If d7=0: bit value meaningless; If d7=1: HSD1 in normal condition If d7=0: HSD1 in normal condition; If d7=1: bit value meaningless If d7=0: bit value meaningless If d7=1: HSD2 in normal condition If d7=0: bit value meaningless If d7=1: HSD2 in normal condition; Normal condition 1 The Diagnostic Register is referred to a test performed in Test mode If d7=0: HSD1 is in overcurrent If d7=1: bit value meaningless If d7=0: bit value meaningless If d7=1: an open load is present on HSD1 If d7=0: bit value meaningless If d7=1: HSD1 is shorted to the supply voltage VDD If d7=0: HSD2 is in overcurrent; If d7=1: bit value meaningless If d7=0: bit value meaningless If d7=1: an open load is present on HSD2 If d7=0: bit value meaningless If d7=1: HSD1 is shorted to the supply voltage VDD Overtemperature protection activated(Tj>150C)
d6
HSD1W1
d5
HSD1W2
d4
HSD1W3
d3
HSD2W1
d2
HSD2W2
d1
HSD1W3
d0
Thermal Warning
SUMMARY OF THE MAIN OPERATIONS Operation A s Test Mode Diagnostic Procedure Start
s s
1) WREN instruction (Fig.11) 2) WSTA instruction (Fig.12)
Operation B s Read the Diagnostic Register Case1: after a Test Mode Diagnostic Procedure Start 1) RDIA instruction (Fig.13) 2) Diagnostic Register output (Fig.13)
s
NOTE: an operation B must follow an operation A. The delay between the end of the operations A to the start of the operations B must be longer than 100S
Operation C s Write the Status Register
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L5953
1) WREN instruction (Fig.11) 2) WSTA instruction (Fig.16) Operation D s Read the Status Register 1) RSTA instruction (Fig.17) 2) Status Register output (Fig.17) Operation E s Diagnostic Procedure Start 1) WREN instruction (Fig.11) 2) WSTA instruction (Fig.14) Operation F s Read the Diagnostic Register Case 2: after a Diagnostic Procedure Start 1) RDIA instruction (Fig.15) 2) Diagnostic Register output (Fig.15) An operation F must follow an operation E if the pin IRQ is not activated. The delay between the Operation E and an Operation F must be longer than 100s. To be recognized, the fault must be present without interruptions during all the delay above mentionned . After an Operation F, the bit s0 of the Status Register is resettled (0) Operation G s Write operation disabled 1) WRDI instruction (Table 1) Operation H s Read the Diagnostic Register case 3: after an IRQ pin activation 1) RDIA instruction (Fig. 15) 2) Diagnostic Register Output (Fig. 15) The delay between the IRQ activation and an Operation F must be longer than 100s Figure 11. Write Enable Latch Sequence
S
00 01 02 03 04 05 06 07
C CPOL=0 CPHA=0 D
HIGH IMPEDANCE
D03AU1483
Q
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L5953
Figure 12. Test Mode Diagnostic Procedure Start (after a Write Enable Latch Sequence, Fig.11)
CPOL=0, CPHA=0 S
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
INSTRUCTION STATUS REGISTER s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0
D
Q
HIGH IMPEDANCE
D03AU1484
Figure 13. Read the Diagnostic registerCase1: after a Test Mode diagnostic procedure start (Fig. 12)
CPOL=0, CPHA=0 S
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15
C
INSTRUCTION
D
DIAGNOSTIC REGISTER OUT HIGH IMPEDANCE
Q
d7
d6
d5
d4
d3
d2
d1
d0
D03AU1485
Figure 14. Diagnostic Procedure Start (after a Write Enable Latch Sequence, operation A)
CPOL=0, CPHA=0 S
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
INSTRUCTION STATUS REGISTER s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0
D
Q
HIGH IMPEDANCE
D03AU1486
Figure 15. Read the Diagnostic RegisterCase2: during the normal working of the L5953 (after a Diagnostic Procedure Start, Fig.14)
CPOL=0, CPHA=0 S
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15
C
INSTRUCTION
D
DIAGNOSTIC REGISTER OUT HIGH IMPEDANCE
Q
d7
d6
d5
d4
d3
d2
d1
d0
D03AU1487
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L5953
Figure 16. Write the Status Register (after a Write Enable Latch Sequence, operation A)
CPOL=0, CPHA=0 S
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
INSTRUCTION STATUS REGISTER s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0
D
Q
HIGH IMPEDANCE
D03AU1488
Figure 17. Read the Status Register
CPOL=0, CPHA=0 S
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
INSTRUCTION
D
STATUS REGISTER OUT HIGH IMPEDANCE
Q
s15
s14
s13
s12
s11
s10
s9
s8
s7
s6
s5
s4
s3
s2
s1
s0
D03AU1489
IRQ - Interrupt Request Pin s It is an open drain pin activated (low) every time a variation occurs in the Diagnostic Register.
s
Purpose: to alert the P that one or more warning bit of the Diagnostic Register has changed from 0 to 1 or from 1 to 0. An activation of this pin puts the bit s0 of the Status Register to 1 (START DIAGNOSTIC) like an Operation E (Diagnostic Procedure Start). Then an Operation F has to be executed without an Operation E before. After an Operation F, the IRQ pin is disactivated, and goes to 1 if connected to a pull-up resistor.
s
s
L5953 - Application Note
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L5953
Figure 18. Block and Application Diagram
C2 C5 D1 C3 C11
VDD S1 W1 S2 W2
C1
VDD-LIN
VDD-SW
STCAP
CT
RES FGND VSTBY C4 ADJ
VOLTAGE WARNING
REG1 ST-BY LINEAR VOLTAGE REGULATOR 3.3-5V/250mA
HSD1 HSD1 PWM STEP DOWN REGULATOR 2.5-10V/1A STRAP C6 DRAINOUT VSW GATEIN D2 L1 Vo R1 C7
HSD2 HSD2
GATEOUT FB VSPI IRQ REG2 LINEAR VOLTAGE REGULATOR 1.5-3.3V/300mA COMP OSCILLATOR & SYNC SWGND GND R4 C9
R2 R3
SPI INTERFACE
C8
Q
D
S
C
VLR C10
FBLR R5 R6
VIN
SYNC
DGND
D01AU1331B
Figure 19. Block Diagram And Application With External Power MOS
C2 C5 D1 C3
VDD S1 W1 S2 W2
C1 VDD-LIN
VDD-SW
STCAP
CT
RES FGND VSTBY C4 ADJ
VOLTAGE WARNING
REG1 ST-BY LINEAR VOLTAGE REGULATOR 3.3-5V/250mA
HSD1 HSD1 PWM STEP DOWN REGULATOR 2.5-10V/1A STRAP C6 DRAINOUT VSW D2 L1 Vo R1 C7
HSD2 HSD2
GATEIN GATEOUT FB VSPI IRQ REG2 LINEAR VOLTAGE REGULATOR 1.5-3.3V/300mA COMP R4 OSCILLATOR & SYNC SWGND GND
M1
R2
SPI INTERFACE
C9
R3
C8 Q D S C VLR C10 FBLR R5 R6 VIN SYNC DGND
D01AU1332B
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L5953
PART LIST on Evaluation Board C1 = 470 F C7 = 470 F ESR=65 m R1 = 2.2 k L1 = 180 H C2 = 220 nF C8 = 56nF R2 = 2 x 1.5 k in parallel C3 = 470 F C9 = 2.7 nF R3 = 10 k D1 = 1N4007 or MBR160 C4 = 10 F C10 = 10 F R4 = 220 k D2 = MBR360 C5 = 1 F C11 = 4.7 nF R5 = 3.3 k R6 = 1 k C6 = 100 nF
REG1 OUTPUT VOLTAGE VSTBY = 5V if pin ADJ left floating VSTBY = 3.3V if pin ADJ is conneted to the pin VSTBY Timing Capacitor The value for this capacitor has to be chosen according the wanted power-on delay Td:
ICT 1 T d C11 = ------------------------------------------------------------( 0.5 VS TB Y ) + V CTL Ry
where ICT1 is the source current used to charge the timing capacitor and VSTBY is the REG1 output voltage. Feedback resistors for REG2
VLR R5 = R6 ------------------------- - 1 V ref, REG 2

where VLR is the required output voltage for REG2. External components for PWM regulator Bootstrap capacitor The suggested value for the bootstrap capacitor is C6 = 100nF Here following you find the criteria for the selection of the inductor L1, the free-wheeling diode D2, the output filter capacitor C7, the feedback resistor R1, R2 and the compensation network R3, C8, R4, C9 to have a Buck regulator working in Continuos mode. Continuous mode operation is recommended in order to reduce the stress of the output capacitor and of the free-wheeling diode. Inductor Selection The minimum value of the inductor L7 has to be so that the maximum inductor current ripple IL,max is 20% to 30% of the maximum load current load Io,max.The maximum ripple is present when the switching frequency is minimum ( fsw,min ) and the input voltage is maximum ( Vin,max ) so the minimum value for the inductor Lmin is :
VO VO 1Lmin = ------------------- 1 - ---------------- ----------------IL, max V i, max fs w, min
Output Capacitor Selection The criteria for the selection of the capacitor C7 is based on the output voltage ripple requirements. The ripple on the output voltage is due to a capacitive contribute, often negligible, equal to
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I L, max V c = -------------------------------------8 C7 f s w, min
and a resistive contribute given by the ESR of the capacitor and which is equal to
V ESR = ESR IL, ma x
VC fixes the value for C7 while VESR limits the ESR of the capacitor.Usually the capacitor is chosen so that the total ripple on the output regulated voltage Vo is equal to 1% of the value of Vo. If Vripple is the maximum allowed voltage ripple on Vo then it should result:
Vripple V c + V ES R
2 2
More often the minimum value of C7 is imposed by other considerations such as to get a good dynamic behaviour of the output voltage in case of large load variations. Free-wheeling diode The diode must withstand an average current Id equal to Id = Ilim ( 1- Dmin ) where Ilim is the current of intervention of the short circuit protection and Dmin is the minimum duty cycle. As Dmin is vey low, the current Id can be assumed equal to Ilim. Compensation Network In continuous mode, the voltage controlled buck converter showes two poles due to the output LC filter and one zero due to the ESR of the output capacitor. The suggested compensation network introduces two zeros and two poles: - the zeros compensate the double poles of the LC filter - one pole compensates the zero due to ESR of the output capacitor - the second pole is nominally located in the origin which means an infinite gain at frequency null. In the reality the DC value of the closed loop gain can not be greater than the DC value of the EA open loop gain and the pole is located at very low frequency. The values for the components of the compensation network can be fixed when the inductor L1 and the output capacitor C7 are chosen. The necessary steps are following: 1.fix the cross-over frequency fC of the overall loop gain. Usually
f c = 0.1 fs w,min
where fsw,min is the minimum switching frequency 2.Calculate the high frequency error amplifier gain
L1 G c = 0.25 f c 2 -----------ESR
3.Chose R3 and calculate
L1 C7 C8 = 2 ----------------------R3
The value for R3 has not to be very high (for example 10K) so to limit the error due to an error amplifier input offset current.
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4.Calculate
R3 R p = -------------------------------------------2 L1 ------------ ------- - 1 E SR C7 VO RA = Rp -----------------------V ref , PWM Rp R2 = -------------------------------Vref,PWM 1 - ---------------------VO

5.Finally calculate
R4 = G C R1
and
L1 C7 C9 = 2 ----------------------R4
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DIM. A a1 a2 a3 b c D (1) D1 E e e3 E1 (1) E2 E3 E4 G H h L N S
MIN. 0.10 0 0.22 0.23 15.80 9.40 13.90
mm TYP.
MAX. 3.60 0.30 3.30 0.10 0.38 0.32 16.00 9.80 14.50
MIN. 0.004 0 0.008 0.009 0.622 0.370 0.547
inch TYP.
MAX. 0.141 0.012 0.130 0.004 0.015 0.012 0.630 0.385 0.570
OUTLINE AND MECHANICAL DATA
0.65 11.05 10.90 5.80 2.90 0 15.50 0.80 11.10 0.429 2.90 6.20 0.228 3.20 0.114 0.10 0 15.90 0.610 1.10 1.10 0.031 10(max.) 8 (max.)
0.0256 0.435 0.437 0.114 0.244 0.126 0.004 0.626 0.043 0.043
PowerSO36
(1): "D" and "E1" do not include mold flash or protrusions - Mold flash or protrusions shall not exceed 0.15mm (0.006 inch) - Critical dimensions are "a3", "E" and "G".
N
N a2 A DETAIL A e3 H lead e A a1 E DETAIL A
c DETAIL B
D a3
36 19
slug BOTTOM VIEW E3
B E2 E1 DETAIL B
0.35 Gage Plane
D1
1
1
8
-C-
S h x 45 b
0.12
M
L
SEATING PLANE G C
AB
PSO36MEC
(COPLANARITY)
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L5953
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2003 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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